The present invention relates to semiconductor circuits, and more specifically to a charge pump which is used in integrated circuits.
As shown in FIG. 1, a prior art charge pump comprises a charge-up circuit 1 and a pull-up circuit 2. Charge-up circuit 1 is formed by an N-channel enhancement mode MOSFET (field effect transistor) 1 whose drain and gate are coupled to a voltage supply 4 at voltage V.sub.CC and whose source is coupled to the drain and gate of an N-channel enhancement mode MOSFET 5 of charge-up circuit 2 and hence to a clock source .phi. through a capacitor 6. The source of MOSFET 5 is coupled to an output terminal 7 which is in turn connected to a suitable utilization circuit. When clock sequence .PHI. switches to low level, the drain of MOSFET 5 is driven by MOSFET 3 and its potential increases as indicated by a dotted line in FIG. 2 to a level V.sub.CC -V.sub.Te (where V.sub.Te is the threshold of MOSFET 3). On reaching this level, MOSFET 3 is turned off. When clock sequence goes high, the voltage at the drain of MOSFET 5 rises sharply to a level V.sub.CC -V.sub.Te +V.sub..phi. is the voltage of the clock sequence) by the action of capacitor 6. This voltage is applied through MOSFET 5 to output terminal 7, producing an output voltage (V.sub.cc -V.sub.Te)+(V.sub..phi. -V.sub.Te) which is indicated by a solid line curve in FIG. 2. To obtain a higher output voltage, pull-up circuits 2-1, 2-2 and 2-3 are cascaded as shown in FIG. 3 such that the second stage is supplied with clock sequence of opposite phase to those of clock sequences supplied to the odd-numbered stages. The voltage at the drain of MOSFET 5-2 is driven to a level equal to (V.sub.CC -V.sub.Te)+(V.phi.-V.sub.Te) when the opposite phase clock is at low level. When the opposite-phase clock goes high, the drain of MOSFET 5-2 is driven to a level equal to (V.sub.CC -V.sub.Te)+(V.phi.-V.sub.Te)+V.sub..phi. which is applied through MOSFET 5-2 to the drain of MOSFET 5-3, which, as a result, rises to a level (V.sub.CC -V.sub.Te)+(V.phi.-V.sub.Te)+(V.phi.-V.sub.Te). The output voltage of this multi-stage circuit is equal to (V.sub.cc -V.sub.Te)+N(V.sub..phi. -V.sub.Te), where N represents the number of cascaded pull-up circuits 2. Usually V.sub..phi. is set equal to V.sub.CC, and the output voltage is 2 V.sub.CC -2 V.sub.Te. Since the threshold voltage V.sub.Te is of a substantial value in comparison with V.sub.CC, the output voltage is too low for some applications. If source voltage V.sub.CC is equal to or lower than the threshold voltage V.sub.Te, the charge-up circuit becomes inoperative, and if V.sub..phi. .ltoreq.V.sub.Te the pull-up circuit becomes inoperative. In either case, the charge pump is inoperative. In addition, a large number of pull-up circuits would be required. For example, if V.sub.CC =V.sub..phi. =1.5 volts, V.sub.Te =1.0 volt, twenty-nine pull-up circuits are required to obtain an output voltage of 15 volts.